Micro-architectural analysis of SPACERAM processing element
Name
42429570-MIT.pdf
Description
Full printable version
Size
29.21 MB
Format
Adobe PDF
Checksum (MD5)
da7070c4d238cbc0bc88328dd73235b2
Author(s)
Pant, Amrit R. (Amrit Raj), 1971-
Advisor(s)
Thomas F. Knight, Jr.
Date Issued
1998
Publisher
Massachusetts Institute of Technology
Abstract
SPACERAM is a SIMD architecture optimized for symbolic spatial computations implemented with multiple banks of DRAM combined with an array of processing elements. Such an architecture facilitates very high processor-memory bandwidth and hence allows for applications requiring orders of magnitude higher processing and update rates per DRAM than any current hardware. The array of processing elements process data coming simultaneously from several memory blocks by applying appropriate shifting and lookup table updates to them. Every processing element contains a permuter which makes it possible to assign data bits from any DRAM block to any functional block within the processing element as specified by controller setup. The lookup table is implemented as a common bus shared by all the processing elements. Micro-architectural analysis of such a processing element presents various possible implementations and trade-off issues associated with them.
Description
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
Includes bibliographical references (leaf 71).
Subjects
Electrical Engineering and Computer Science
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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