Fabrication and process characterization of atom transistor chips
Name
Chuang-2009-Fabrication and process characterization of atom transistor chips.pdf
Size
1.7 MB
Format
Adobe PDF
Checksum (MD5)
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Author(s)
Bright, V. M.
Anderson, D. Z.
Salim, E. A.
Chuang, H. C.
Vuletic, Vladan
Date Issued
October 2009
Journal
Proceedings of the Solid-State Sensors, Actuators and Microsystems Conference, 2009
Publisher
Institute of Electrical and Electronics Engineers
Citation
Chuang, H.C. et al. “Fabrication and process characterization of atom transistor chips.” Solid-State Sensors, Actuators and Microsystems Conference, 2009. TRANSDUCERS 2009. International. 2009. 1305-1308. © 2009 IEEE
Version
Final published version
Abstract
This paper describes the design and fabrication of an atom chip for atom tunneling experiments. A fabrication process was developed that uses a combination of UV-optical and Electron-Beam lithography to pattern micrometer and nanometer scale copper wires on a single chip. The minimum wire width fabricated in this work is 200 nm. The wires can carry current densities of more than 7.5times10[superscript 7] A/cm[superscript 2]. The electrical current tests establish the feasibility of realizing chip-based atom tunneling experiments.
Subjects
Atom Chips
Atom Transistor
Atom Tunneling
Bose-Einstein Condensation (BEC)
E-Beam Lithography
Suspended Nanowires
MIT Department
Massachusetts Institute of Technology. Department of Physics
MIT-Harvard Center for Ultracold Atoms
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/SENSOR.2009.5285870
