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Compaction with Automatic Job Introduction

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MIT-LCS-TR-372.pdf

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Author(s)
Maley, F. Miller
Advisor(s)
Leiserson, Charles E.
Date Issued
November 1986
Series/Report no.
MIT-LCS-TR-372
Abstract
This thesis presents an algorithm for one-dimensional compaction of VLSI layouts. It differs from older methods in treating wires not as objects to be moved, but as constraints on the positions of other circuit components. These constraints are determined for each wiring layer using the theory of planar routing.
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