Accelerating RTL Simulation with Hardware-Software Co-Design
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3613424.3614257.pdf
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Author(s)
Elsabbagh, Fares
Sheikhha, Shabnam
Ying, Victor
Nguyen, Quan
Emer, Joel
Sanchez, Daniel
Date Issued
October 28, 2023
Publisher
ACM|56th Annual IEEE/ACM International Symposium on Microarchitecture
Citation
Elsabbagh, Fares, Sheikhha, Shabnam, Ying, Victor, Nguyen, Quan, Emer, Joel et al. 2023. "Accelerating RTL Simulation with Hardware-Software Co-Design."
Version
Final published version
Abstract
Fast simulation of digital circuits is crucial to build modern chips. But RTL (Register-Transfer-Level) simulators are slow, as they cannot exploit multicores well. Slow simulation lengthens chip design time and makes bugs more frequent.
We present ASH, a parallel architecture tailored to simulation workloads. ASH consists of a tightly codesigned hardware architecture and compiler for RTL simulation. ASH exploits two key opportunities. First, it performs dataflow execution of small tasks to leverage the fine-grained parallelism in simulation workloads. Second, it performs selective event-driven execution to run only the fraction of the design exercised each cycle, skipping ineffectual tasks. ASH hardware provides a novel combination of dataflow and speculative execution, and ASH’s compiler features several novel techniques to automatically leverage this hardware.
We evaluate ASH in simulation using large Verilog designs. An ASH chip with 256 simple cores is gmean 1,485 × faster than 1-core Verilator, and it is 32 × faster than parallel Verilator on a server CPU with 32 complex cores, while using 3 × less area.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
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DOI of Published Version
https://doi.org/10.1145/3613424.3614257
