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  4. GaN remote epitaxy on a pristine graphene buffer layer via controlled graphitization of SiC

GaN remote epitaxy on a pristine graphene buffer layer via controlled graphitization of SiC

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Author(s)
Lee, Seokje
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Kim, Jekyung
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Park, Bo-In
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Kim, Han Ik
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Lim, Changhyun
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Lee, Eunsu
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Yang, Jeong Yong
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Choi, Joonghoon
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Hong, Young Joon
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Chang, Celesta S
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Date Issued
December 16, 2024
Journal
Applied Physics Letters
Publisher
AIP Publishing
Citation
Seokje Lee, Jekyung Kim, Bo-In Park, Han Ik Kim, Changhyun Lim, Eunsu Lee, Jeong Yong Yang, Joonghoon Choi, Young Joon Hong, Celesta S. Chang, Hyun S. Kum, Jeehwan Kim, Kyusang Lee, Hyunseok Kim, Gyu-Chul Yi; GaN remote epitaxy on a pristine graphene buffer layer via controlled graphitization of SiC. Appl. Phys. Lett. 16 December 2024; 125 (25): 252102.
Version
Final published version
Abstract
Freestanding semiconductor membranes hold significant potential for heterogeneous integration technology and flexible electronics. Remote epitaxy, which leverages electrostatic interactions between epilayers and substrates through two-dimensional (2D) materials such as graphene, offers a promising solution for fabricating freestanding single-crystal membranes. Although the thinness, uniformity, and cleanness of 2D materials need to be meticulously controlled to enable the remote epitaxy of high-quality thin films, attaining such ideal growth templates has been challenging thus far. In this study, we demonstrate a controlled graphitization method to form a pristine graphene buffer layer (GBL) directly on SiC substrates and utilize this GBL template for GaN remote epitaxy. The quasi-two-dimensional GBL layer obtained by the method is completely free of damage or contamination, facilitating strong epitaxial interaction between the GaN epilayer and the SiC substrate. Furthermore, we reveal that a two-step growth of GaN on this GBL template enables the formation of single-crystal GaN epilayers and their exfoliation. Thus, this study represents an important step toward developing high-quality, freestanding semiconductor membranes.
MIT Department
Massachusetts Institute of Technology. Research Laboratory of Electronics
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
https://dspace.mit.edu/handle/1721.1/174461
DOI of Published Version
https://doi.org/10.1063/5.0235653
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