Fast inference of Boosted Decision Trees in FPGAs for particle physics
Name
Summers_2020_J._Inst._15_P05026.pdf
Description
Published version
Size
1.01 MB
Format
Adobe PDF
Checksum (MD5)
30356086b6566bdf8c72af05ed1577d1
Author(s)
Summers, S
Guglielmo, G Di
Duarte, J
Harris, P
Hoang, D
Jindariani, S
Kreinar, E
Loncar, V
Ngadiuba, J
Pierini, M
Date Issued
2020
Journal
Journal of Instrumentation
Publisher
IOP Publishing
Version
Final published version
Abstract
We describe the implementation of Boosted Decision Trees in the hls4ml library, which allows the translation of a trained model into FPGA firmware through an automated conversion process. Thanks to its fully on-chip implementation, hls4ml performs inference of Boosted Decision Tree models with extremely low latency. With a typical latency less than 100 ns, this solution is suitable for FPGA-based real-time processing, such as in the Level-1 Trigger system of a collider experiment. These developments open up prospects for physicists to deploy BDTs in FPGAs for identifying the origin of jets, better reconstructing the energies of muons, and enabling better selection of rare signal processes.
MIT Department
Massachusetts Institute of Technology. Department of Physics
Terms of Use
Creative Commons Attribution 3.0 unported license
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1088/1748-0221/15/05/P05026
