Emulation of microprocessor memory systems using the RAMP design framework
Name
243608011-MIT.pdf
Description
Full printable version
Size
2.55 MB
Format
Adobe PDF
Checksum (MD5)
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Author(s)
Khan, Asif I. (Asif Imtiaz)
Advisor(s)
Krste Asanović.
Date Issued
2008
Publisher
Massachusetts Institute of Technology
Abstract
With the computer hardware industry and the academic world focused on multiprocessor systems, the RAMP project is aiming to provide the infrastructure for supporting high-speed emulation of large scale, massively-parallel multiprocessor systems using FPGAs. The RAMP design framework provides the platform for building this infrastructure. This research utilizes this design framework to emulate various microprocessor memory systems through a model built in an FPGA. We model both the latency and the bandwidth of memory systems through a parameterized emulation platform, thereby, demonstrating the validity of the design framework. We also show the efficiency of the framework through an evaluation of the utilized FPGA resources.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 49-50).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
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