Performance Metrics and Empirical Results of a PUF Cryptographic Key Generation ASIC
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Devadas-Performance metrics.pdf
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383.86 KB
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Author(s)
Yu, Meng-Day (Mandel)
Sowell, Richard
Singh, Alok
M’Raihi, David
Devadas, Srinivas
Date Issued
June 2012
Journal
Proceedings of the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2012
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
(Mandel) Yu, Meng-Day et al. “Performance Metrics and Empirical Results of a PUF Cryptographic Key Generation ASIC.” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2012. 108–115.
Version
Author's final manuscript
Abstract
We describe a PUF design with integrated error correction that is robust to various layout implementations and achieves excellent and consistent results in each of the following four areas: Randomness, Uniqueness, Bias and Stability. 133 PUF devices in 0.13 μm technology encompassing seven circuit layout implementations were tested. The PUF-based key generation design achieved less than 0.58 ppm failure rates with 50%+ stability safety margin. 1.75M error correction blocks ran error-free under worst-case V/T corners (±10% V, 125°C/-65°C) and under voltage extremes of ±20% V. All PUF devices demonstrated excellent NIST-random behavior (99 cumulative percentile), a criterion used to qualify random sources for use as keying material for cryptographic-grade applications.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike 3.0
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DOI of Published Version
https://doi.org/10.1109/HST.2012.6224329
