Inherent limitations of hybrid transactional memory
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Author(s)
Alistarh, Dan
Kuznetsov, Petr
Ravi, Srivatsan
Kopinsky, Justin
Shavit, Nir N.
Date Issued
June 2017
Journal
Distributed Computing
Publisher
Springer Berlin Heidelberg
Citation
Alistarh, Dan, et al. “Inherent Limitations of Hybrid Transactional Memory.” Distributed Computing, vol. 31, no. 3, June 2018, pp. 167–85.
Version
Author's final manuscript
Abstract
Several hybrid transactional memory (HyTM) schemes have recently been proposed to complement the fast, but best-effort nature of hardware transactional memory with a slow, reliable software backup. However, the costs of providing concurrency between hardware and software transactions in HyTM are still not well understood. In this paper, we propose a general model for HyTM implementations, which captures the ability of hardware transactions to buffer memory accesses. The model allows us to formally quantify and analyze the amount of overhead (instrumentation) caused by the potential presence of software transactions. We prove that (1) it is impossible to build a strictly serializable HyTM implementation that has both uninstrumented reads and writes, even for very weak progress guarantees, and (2) the instrumentation cost incurred by a hardware transaction in any progressive opaque HyTM is linear in the size of the transaction’s data set. We further describe two implementations which exhibit optimal instrumentation costs for two different progress conditions. In sum, this paper proposes the first formal HyTM model and captures for the first time the trade-off between the degree of hardware-software TM concurrency and the amount of instrumentation overhead. Keywords: hardware transactional memory, Instrumentation, Lower bounds
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
https://doi.org/10.1007/s00446-017-0305-3
