Verifying Hardware Security Modules With True Random NumberGenerators
Name
zhao-kzhao02-meng-eecs-2024-thesis.pdf
Description
Thesis PDF
Size
1.66 MB
Format
Adobe PDF
Checksum (MD5)
1e4d5160f985c3f946355708e6dcb9d4
Author(s)
Zhao, Katherine
Advisor(s)
Zeldovich, Nickolai
Athalye, Anish
Date Issued
May 2024
Publisher
Massachusetts Institute of Technology
Abstract
Hardware security modules (HSMs) are powerful tools in building secure computer systems, allowing developers to factor out security-critical code to separate devices. Because HSMs usually work with sensitive data, it is crucial that we are able to verify that they are secure. Many HSMs today also include true random number generators (TRNGs) as part of their architecture to seed cryptographic functions for generating keys, creating nonces, padding, and more. This thesis presents a definition of Information-Preserving Refinement with Randomness (IPRR) that captures the idea that a HSM with a TRNG is correct and is secure from timing side channel attacks. We additionally construct a strategy to prove IPRR, and develop Karatroc, a tool for verifying that a HSM satisfies IPRR. Through the creation and evaluation of Karatroc, we demonstrate the ability to verify HSMs with TRNGs without incurring significant added cost in performance and proof length as compared to existing proof methods.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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