A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier
Name
Sinangil-2009-A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier.pdf
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Author(s)
Sinangil, Mahmut Ersin
Verma, Naveen
Chandrakasan, Anantha P.
Date Issued
November 2009
Journal
IEEE Asian Solid-State Circuits Conference (A-SSCC)
Publisher
Institute of Electrical and Electronics Engineers
Citation
Sinangil, M.E., N. Verma, and A.P. Chandrakasan. “A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier.” Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian. 2009. 225-228. © 2009, IEEE
Version
Final published version
Abstract
8T bit-cells hold great promise for overcoming device
variability in deeply scaled SRAMs and enabling aggressive
voltage scaling for ultra-low-power. This paper presents an array
architecture and circuits with minimal area overhead to allow
column-interleaving while eliminating the half-select problem.
This enables sense-amplifier sharing and soft-error immunity.
A reference selection loop is designed and implemented in the
column circuitry. By choosing one of the two reference voltages
for each sense-amplifier in a pseudo-differential scheme, selection
loop effectively reduces input offset. 8T test array fabricated in
45nm CMOS achieves functionality from 1.1V to below 0.5V.
Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while
consuming 12.9 mW and 46 μW [mu W] respectively.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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DOI of Published Version
https://doi.org/10.1109/ASSCC.2009.5357219
