Cimple: instruction and memory level parallelism: a DSL for uncovering ILP and MLP
Name
1807.01624.pdf
Description
Submitted version
Size
762.89 KB
Format
Adobe PDF
Checksum (MD5)
0328495ef010d1d46f9abee33f9f07d2
Author(s)
Kiriansky, Vladimir
Xu, Haoran
Rinard, Martin
Amarasinghe, Saman
Date Issued
November 2018
Journal
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques
Publisher
Association of Computing Machinery
Citation
Kiriansky, Vladimir et al. "Cimple: instruction and memory level parallelism: a DSL for uncovering ILP and MLP." Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques (November 2018): 30 © 2018 Association for Computing Machinery
Version
Original manuscript
Abstract
Modern out-of-order processors have increased capacity to exploit instruction level parallelism (ILP) and memory level parallelism (MLP), e.g., by using wide superscalar pipelines and vector execution units, as well as deep buffers for inflight memory requests. These resources, however, often exhibit poor utilization rates on workloads with large working sets, e.g., in-memory databases, key-value stores, and graph analytics, as compilers and hardware struggle to expose ILP and MLP from the instruction stream automatically. In this paper, we introduce the IMLP (Instruction and Memory Level Parallelism) task programming model. IMLP tasks execute as coroutines that yield execution at annotated long-latency operations, e.g., memory accesses, divisions, or unpredictable branches. IMLP tasks are interleaved on a single thread, and integrate well with thread parallelism and vectorization. Our DSL embedded in C++, Cimple, allows exploration of task scheduling and transformations, such as buffering, vectorization, pipelining, and prefetching. We demonstrate state-of-the-art performance on core algorithms used in in-memory databases that operate on arrays, hash tables, trees, and skip lists. Cimple applications reach 2.5× throughput gains over hardware multithreading on a multi-core, and 6.4× single thread speedup.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1145/3243176.3243185
