Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip
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Peh_Enabling System-level.pdf
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687.7 KB
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Author(s)
Aisopos, Konstantinos
Chen, Chia-Hsin
Peh, Li-Shiuan
Date Issued
June 2011
Journal
Proceedings of the 48th Design Automation Conference (DAC '11)
Publisher
Association for Computing Machinery (ACM)
Citation
Konstantinos Aisopos, Chia-Hsin Chen, and Li-Shiuan Peh. 2011. Enabling system-level modeling of variation-induced faults in networks-on-chips. In Proceedings of the 48th Design Automation Conference (DAC '11). ACM, New York, NY, USA, 930-935.
Version
Author's final manuscript
Abstract
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike 3.0
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DOI of Published Version
https://doi.org/10.1145/2024724.2024931
