Circuits and algorithms for pipelined ADCs in scaled CMOS technologies
Name
288990071-MIT.pdf
Description
Full printable version
Size
38.68 MB
Format
Adobe PDF
Checksum (MD5)
8ac29cc9ac654adadf9def357c8a55cc
Author(s)
Brooks, Lane Gearle, 1975-
Advisor(s)
Hae-Seung Lee and Gregory Wornell.
Date Issued
2008
Publisher
Massachusetts Institute of Technology
Abstract
CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally used in switched capacitor circuits. This research involves two complementary methods for addressing scaling issues. First is the development of two blind digital calibration techniques. Decision Boundary Gap Estimation (DBGE) removes static non-linearities and Chopper Offset Estimation (COE) nulls offsets in pipelined ADCs. Second is the development of circuits for a new architecture called zero-crossing based circuits (ZCBC) that is more amenable to scaling trends. To demonstrate these circuits and algorithms, two different ADCs were designed: an 8 bit, 200MS/s in TSMC 180nm technology, and a 12 bit, 50 MS/s in IBM 90nm technology. Together these techniques can be enabling technologies for both pipelined ADCs and general mixed signal design in deep sub-micron technologies.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
MIT Barker Engineering Library copy: printed in pages.
Also issued printed in pages.
Includes bibliographical references (leaves 179-184).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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