Comparison of high level design methodologies for algorithmic IPs : Bluespec and C-based synthesis
Name
426039412-MIT.pdf
Description
Full printable version
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1.74 MB
Format
Adobe PDF
Checksum (MD5)
89483ec47d96e7bbe2ba70c1a93cc5ec
Author(s)
Agarwal, Abhinav
Advisor(s)
Arvind.
Date Issued
2009
Publisher
Massachusetts Institute of Technology
Abstract
High level hardware design of Digital Signal Processing algorithms is an important design problem for decreasing design time and allowing more algorithmic exploration. Bluespec is a Hardware Design Language (HDL) that allows designers to express intended microarchitecture through high-level constructs. C-based design tools directly generate hardware from algorithms expressed in C/C++. This research compares these two design methodologies in developing hardware for Reed-Solomon decoding algorithm under area and performance metrics. This work illustrates that C-based design flow may be effective in early stages of the design development for fast prototyping. However, the Bluespec design flow produces hardware that is more customized for performance and resource constraints. This is because in later stages, designers need to have close control over the hardware structure generated that is a part of HDLs like Bluespec, but is difficult to express under the constraints of sequential C semantics.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
Includes bibliographical references (leaves 37-39).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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