Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators
Name
1912.12167.pdf
Description
Accepted version
Size
566 KB
Format
Unknown
Checksum (MD5)
411e9c469de5fba055117f56590c18c2
Author(s)
Yang, Tien-Ju
Sze, Vivienne
Date Issued
December 2020
Journal
Technical Digest - International Electron Devices Meeting, IEDM
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
2020. "Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators." Technical Digest - International Electron Devices Meeting, IEDM, 2019-December.
Version
Author's final manuscript
Abstract
© 2019 IEEE. This paper describes various design considerations for deep neural networks that enable them to operate efficiently and accurately on processing-in-memory accelerators. We highlight important properties of these accelerators and the resulting design considerations using experiments conducted on various state-of-the- art deep neural networks with the large-scale ImageNet dataset.
MIT Department
Massachusetts Institute of Technology. Microsystems Technology Laboratories
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/IEDM19573.2019.8993662
