Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
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Accepted version
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494.7 KB
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Author(s)
Lee, Kwang Hong
Bao, Shuyu
Zhang, Li
Kohen, David
Fitzgerald, Eugene A
Tan, Chuan Seng
Date Issued
July 2016
Journal
Applied Physics Express
Publisher
Japan Society of Applied Physics
Citation
Lee, Kwang Hong et al. "Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process." Applied Physics Express, 9, 8 (July 2016) © 2016 The Japan Society of Applied Physics.
Version
Author's final manuscript
Abstract
The integration of III-V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI-GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI-GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.
MIT Department
Singapore-MIT Alliance in Research and Technology (SMART)
Massachusetts Institute of Technology. Department of Materials Science and Engineering
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.7567/apex.9.086501
