Non-linear operating point statistical analysis for local variations in logic timing at low voltage
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Chandrakasan-Non-linear operating.pdf
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Author(s)
Rithe, Rahulkumar Jagdish
Gu, Jie
Wang, Alice
Datla, Satyendra
Gammie, Gordon
Buss, Dennis
Chandrakasan, Anantha P.
Date Issued
April 2010
Journal
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2010
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Rahul Rithe eta l. "Non-linear operating point statistical analysis for local variations in logic timing at low voltage." Design, Automation & Test in Europe Conference & Exhibition, 965 - 968, 2010. © 2010 EDAA
Version
Final published version
Abstract
For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28 nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5456911&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DNon-linear+Operating+Point+Statistical+Analysis+for+Local+Variations+in+Logic+Timing+at+Low+Voltage
