FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics
Name
Vitale-2010-FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics.pdf
Size
1.27 MB
Format
Adobe PDF
Checksum (MD5)
bc72f2b807c70b8a74ef31d10e36ffbb
Author(s)
Vitale, Steven A.
Wyatt, Peter W.
Checka, Nisha
Kedzierski, Jakub T.
Keast, Craig L.
Date Issued
February 2010
Journal
Proceedings of the IEEE
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Vitale, S.A. et al. “FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics.” Proceedings of the IEEE 98.2 (2010): 333–342. © 2010 IEEE
Version
Final published version
Abstract
Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.
MIT Department
Lincoln Laboratory
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
DOI of Published Version
http://dx.doi.org/10.1109/jproc.2009.2034476
