A low phase noise ring oscillator phase-locked loop for wireless applications
Name
62559899-MIT.pdf
Description
Full printable version
Size
4.47 MB
Format
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Checksum (MD5)
64c94c8e16037fda1f5863cd64f32eb2
Author(s)
Weltin-Wu, Colin
Advisor(s)
James K. Roberge.
Date Issued
2005
Publisher
Massachusetts Institute of Technology
Abstract
This thesis describes the circuit level design of a 900MHz [Sigma][Detta] ring oscillator based phase-locked loop using 0.35[mu]m technology. Multiple phase noise theories are considered giving insight into low phase-noise voltage controlled oscillator design. The circuit utilizes a fully symmetric differential voltage controlled oscillator with cascode current starved inverters to reduces current noise. A compact multi-modulus prescaler is presented, based on modified true single-phase clock flip-flops with integrated logic. A fully differential charge pump with switched-capacitor common mode feedback is utilized in conjunction with a nonlinear phase-frequency detector for accelerated acquisition time.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 129).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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