Memory-mapping support for reducer hyperobjects
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Leiserson_Memory-mapping.pdf
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203.03 KB
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bd05c22e9f44644cbfe6e135d7bad5d1
Author(s)
Lee, I-Ting Angelina
Shafi, Aamir
Leiserson, Charles E.
Date Issued
June 2012
Journal
Proceedinbgs of the 24th ACM symposium on Parallelism in algorithms and architectures (SPAA '12)
Publisher
Association for Computing Machinery (ACM)
Citation
I-Ting Angelina Lee, Aamir Shafi, and Charles E. Leiserson. 2012. Memory-mapping support for reducer hyperobjects. In Proceedings of the twenty-fourth annual ACM symposium on Parallelism in algorithms and architectures (SPAA '12). ACM, New York, NY, USA, 287-297.
Version
Author's final manuscript
Abstract
Reducer hyperobjects (reducers) provide a linguistic abstraction for dynamic multithreading that allows different branches of a parallel program to maintain coordinated local views of the same nonlocal variable. In this paper, we investigate how thread-local memory mapping (TLMM) can be used to improve the performance of reducers. Existing concurrency platforms that support reducer hyperobjects, such as Intel Cilk Plus and Cilk++, take a hypermap approach in which a hash table is used to map reducer objects to their local views. The overhead of the hash table is costly --- roughly 12x overhead compared to a normal L1-cache memory access on an AMD Opteron 8354. We replaced the Intel Cilk Plus runtime system with our own Cilk-M runtime system which uses TLMM to implement a reducer mechanism that supports a reducer lookup using only two memory accesses and a predictable branch, which is roughly a 3x overhead compared to an ordinary L1-cache memory access. An empirical evaluation shows that the Cilk-M memory-mapping approach is close to 4x faster than the Cilk Plus hypermap approach. Furthermore, the memory-mapping approach admits better locality than the hypermap approach during parallel execution, which allows an application using reducers to scale better.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1145/2312005.2312056
