InGaAs self-aligned HEMT for logic applications
Name
272356922-MIT.pdf
Description
Full printable version
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30.97 MB
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Checksum (MD5)
fbecf94a6ec9d175b093cf7a678f6c38
Author(s)
Waldron, Niamh, 1974-
Advisor(s)
Jesús A. del Alamo.
Alternative Title
InGaAs self-aligned high electron mobility transistor for logic applications
Date Issued
2007
Publisher
Massachusetts Institute of Technology
Abstract
As CMOS scaling approaches the end of the roadmap it has become a matter of great urgency to explore alternative options to conventional Si devices for logic applications. The high electron mobilities of III-V based compounds makes them an attractive option for use as a channel material. Of these materials, InGaAs offers the best balance between a mature technology and high mobility. InGaAs high electron mobility transistors (HEMTs) have already been shown to hold great promise for logic devices but they are typically not self-aligned nor enhancement mode and as such are not suitable for scaled VLSI applications. In this work a novel self-aligned device architecture for InGaAs HEMT devices is proposed and demonstrated. The key feature of the process is a non-alloyed a W ohmic layer that is separated from the gate by means of an air spacer. The gate to source metal distance is reduced to 60 nm, a 20x improvement over conventional designs where the source to drain distance is typically 1.5 to 2 /Lm. A detailed analysis of the source resistance was carried out and the heterojunction barrier resistance was determined to be the dominant resistance component. Two methods of changing the device threshold voltage are investigated. In the first F is used to passivate Si donors in the insulator layer. In the second the insulator is thinned by means of a dry etch. No degradation of the source resistance was observed using this method, which is an improvement over previous results using wet chemical etching. A 90 nm self-aligned enhancement-mode device with a vertically scaled insulator thickness of 5 nm was fabricated. The device has outstanding logic figures of merit with a VT of 60 mV, g, of 1.3 S/mm, SS of 71 mV/dec, DIBL of 55 mV/V and an I,/Ileak ratio of 2x103.
(cont.) These values are outstanding when compared to state of-the-art Si devices. The relatively low In/Ileak ratio is a consequence of operating a Schottky gate device in enhancement mode. Ultimately a high-k gate dielectric solution will be required.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
Includes bibliographical references (p. 123-132).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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