Thermal Modeling and Device Noise Properties of Three-Dimensional-SOI Technology
Name
Chen-2009-Thermal Modeling and.pdf
Size
1.06 MB
Format
Adobe PDF
Checksum (MD5)
595aec979533b65a3cf796912e2445d6
Author(s)
Chen, Tze Wee
Chun, Jung-Hoon
Lu, Yi-Chang
Navid, Reza
Wang, Wei
Chen, Chang-Lee
Dutton, Robert W.
Date Issued
March 2009
Journal
IEEE Transactions on Electron Devices
Publisher
Institute of Electrical and Electronics Engineers
Citation
Tze Wee Chen et al. “Thermal Modeling and Device Noise Properties of Three-Dimensional–SOI Technology.” Electron Devices, IEEE Transactions on 56.4 (2009): 656-664. © 2009 Institute of Electrical and Electronics Engineers
Version
Final published version
Abstract
Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-mum three-dimensional (3-D)-SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D-SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D-SOI technology are also characterized and compared with conventional bulk CMOS technology.
Subjects
three-dimensional (3-D) integrated circuit
thermal modeling
electrothermal
Device noise
3-D silicon-on-insulator
MIT Department
Lincoln Laboratory
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
DOI of Published Version
http://dx.doi.org/10.1109/TED.2009.2014188
