50-nm E-mode In[subscript 0.7]Ga[subscript 0.3]As PHEMTs on 100-mm InP substrate with f[subscript max] > 1 THz
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del Alamo-50-nm E-mode.pdf
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Author(s)
del Alamo, Jesus A.
Kim, Dae-Hyun
Chen, Peter
Ha, Wonill
Urteaga, Miguel
Brar, B.
Date Issued
December 2010
Journal
Proceedings of the IEEE International Electron Devices Meeting (IEDM), 2010
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Kim, Dae-Hyun et al. “50-nm E-mode In[subscript 0.7]IEEE International Electron Devices Meeting (IEDM), 2010. 30.6.1–30.6.4. © Copyright 2010 IEEE
Version
Final published version
Abstract
We have demonstrated 50-nm enhancement-mode (E-mode) In[subscript 0.7]Ga[subscript 0.3]As PHEMTs with f[subscript max] in excess of 1 THz. The devices feature a Pt gate sinking process to effectively thin down the In[subscript 0.52]Al[subscript 0.48]As barrier layer, together with a two-step recess process. The fabricated device with L[subscript g] = 50-nm exhibits V[subscript T] = 0.1 V, g[subscript m,max] = 1.75 mS/μm, f[subscript T] = 465 GHz and f[subscript max] = 1.06 THz at a moderate value of V[subscript DS] = 0.75 V. In addition, we have physically modeled the abnormal peaky behavior in Mason's unilateral gain (U[subscript g]) at high values of VDS. A revised small signal model that includes a shunting R[subscript gd-NDR] with negative value successfully describes the behavior of the device from 1 to 67 GHz.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
https://doi.org/10.1109/IEDM.2010.5703453
