29.8 SHARC: Self-Healing Analog with RRAM and CNFETs
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Author(s)
Amer, Aya G.
Ho, Rebecca
Hills, Gage Krieger
Chandrakasan, Anantha P
Shulaker, Max M.
Date Issued
February 2019
Journal
2019 IEEE International Solid- State Circuits Conference - (ISSCC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Amer, Aya G. et al. "29.8 SHARC: Self-Healing Analog with RRAM and CNFETs." 2019 IEEE International Solid- State Circuits Conference - (ISSCC), February 2019, San Francisco, California, USA, Institute of Electrical and Electronics Engineers (IEEE) © 2019 IEEE
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Author's final manuscript
Abstract
Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology for energy-efficient electronics (Fig. 29.8.1). Despite this promise, CNTs are subject to substantial inherent imperfections; every ensemble of CNTs includes some percentage of metallic CNTs (m-CNTs). m-CNTs result in conductive shorts between CNFET source and drain, resulting in excessive leakage and degraded (potentially incorrect) circuit functionality (Fig. 29.8.1). Several techniques have been developed to remove the majority of m-CNTs (no technique today removes 100% of m-CNTs). While these techniques enabled the first digital CNFET circuits, it is still not possible to realize large-scale CNFET analog or mixed-signal CNFET circuits due to m-CNTs. As shown in Fig. 29.8.1, while a digital logic gate can still function correctly in the presence of a small fraction of m-CNTs (but with degraded resilience to noise) [1], a single m-CNT in an analog circuit can result in catastrophic failure (e.g., degrading amplifier gain resulting in functional failure of circuit blocks such as ADCs and DACs) 1 . This paper presents a circuit design technique, Self-Healing Analog with RRAM and CNFETs (SHARC), that leverages the programmability of non-volatile resistive RAM (RRAM) to automatically “self-heal” analog circuits in the presence of m-CNTs. Using SHARC, we experimentally demonstrate analog CNFET circuits robust to m-CNTs as well as the first mixed-signals CNFET sub-system (4-bit DAC and SAR ADC; these are the largest reported complementary (CMOS) CNFET circuit demonstrations to-date).
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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DOI of Published Version
http://dx.doi.org/10.1109/isscc.2019.8662377
