WSIM configurable digital signal processor simulator/debugger
Name
57146137-MIT.pdf
Description
Full printable version
Size
301.13 KB
Format
Adobe PDF
Checksum (MD5)
7ca38a40b1c1bf80a5c85ece9099e19b
Author(s)
Ni, Wayland, 1982-
Advisor(s)
Charlie Sakamaki and Chris Terman.
Alternative Title
WSIM configurable DSP simulator/debugger
Date Issued
2004
Publisher
Massachusetts Institute of Technology
Abstract
This M.Eng. Thesis presents a design and implementation of a full-featured configurable Digital Signal Processor (DSP) simulator/debugger. The user will be able to set configurations in order to model a specific architecture design. The simulator will have a command interpreter to listen to and process commands given by the user. When supplied with an assembly program, the simulator will allow the user to step through the execution of the program cycle by cycle, as well as calculate statistics like instruction, resource, and cache profiling. Some of the main features of the simulator are a multiply-accumulate unit, memory with direct and indirect offset addressing, and loop instructions.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (leaf 53).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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