FPGA-based true random number generation using circuit metastability with adaptive feedback control
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Devadas-FPGA-based true.pdf
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Author(s)
Majzoobi, Mehrdad
Koushanfar, Farinaz
Devadas, Srinivas
Date Issued
September 2011
Journal
Cryptographic Hardware and Embedded Systems – CHES 2011
Publisher
Springer Berlin / Heidelberg
Citation
Majzoobi, Mehrdad, Farinaz Koushanfar, and Srinivas Devadas. “FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control.” Cryptographic Hardware and Embedded Systems – CHES 2011. Ed. Bart Preneel & Tsuyoshi Takagi. LNCS Vol. 6917. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. 17–32.
Version
Author's final manuscript
Abstract
The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Metastability is achieved by using precise programmable delay lines (PDL) that accurately equalize the signal arrival times to flip-flops. The PDLs are capable of adjusting signal propagation delays with resolutions higher than fractions of a pico second. In addition, a real time monitoring system is utilized to assure a high degree of randomness in the generated output bits, resilience against fluctuations in environmental conditions, as well as robustness against active adversarial attacks. The monitoring system employs a feedback loop that actively monitors the probability of output bits; as soon as any bias is observed in probabilities, it adjusts the delay through PDLs to return to the metastable operation region. Implementation on Xilinx Virtex 5 FPGAs and results of NIST randomness tests show the effectiveness of our approach.
Description
13th International Workshop, Nara, Japan, September 28 – October 1, 2011. Proceedings
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
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Creative Commons Attribution-Noncommercial-Share Alike 3.0
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DOI of Published Version
https://doi.org/10.1007/978-3-642-23951-9_2
