Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs
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del Alamo_Multiscale metrology.pdf
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Author(s) • • • •
Kharche, Neerav
Klimeck, Gerhard
Kim, Dae-Hyun
Luisier, Mathieu
del Alamo, Jesus A.
Date Issued
May 2011
Journal
IEEE Transactions on Electron Devices
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Kharche, Neerav, Gerhard Klimeck, Dae-Hyun Kim, Jesus A. del Alamo, and Mathieu Luisier. “Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs.” IEEE Transactions on Electron Devices 58, no. 7 (n.d.): 1963–1971.
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Author's final manuscript
Abstract
A simulation methodology for ultra-scaled InAs quantum well field-effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, an atomistic sp[superscript 3]d[superscript 5]s* tight-binding model is used to compute channel effective masses, and a 2-D real-space effective mass-based ballistic quantum transport model is employed to simulate three-terminal current-voltage characteristics including gate leakage. The simulation methodology is first benchmarked against experimental I-V data obtained from devices with gate lengths ranging from 30 to 50 nm. A good quantitative match is obtained. The calibrated simulation methodology is subsequently applied to optimize the design of a 20 nm gate length device. Two critical parameters have been identified to control the gate leakage current of the QWFETs, i) the geometry of the gate contact (curved or square) and ii) the Schottky barrier height at the gate metal contact. In addition to pushing the threshold voltage toward an enhancement mode operation, a higher Schottky barrier at gate metal contact can help suppress the gate leakage and enable aggressive insulator scaling.
MIT Department
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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DOI of Published Version
https://doi.org/10.1109/ted.2011.2144986