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  5. Implementation of delay and power reduction in deep sub-micron buses using coding

Implementation of delay and power reduction in deep sub-micron buses using coding

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Author(s)
Konstantakopoulos, Theodoros K., 1977-
Advisor(s)
Anantha P. Chandrakasan.
Date Issued
2002
Publisher
Massachusetts Institute of Technology
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references (p. 73-74).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Persistent DSpace Link
http://hdl.handle.net/1721.1/87204
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