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A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems
Name
sensors-18-02709.pdf
Size
4.26 MB
Format
Adobe PDF
Checksum (MD5)
30756b42c5c7b59d9135a5cd9b4edc63
Author(s)
Kim, Sang-Hoon
Shin, Hoon
Jeong, Youngkyun
Lee, June-Hee
Choi, Jaehyuk
Chun, Jung-Hoon
Journal
Sensors
Citation
Kim, Sang-Hoon, Hoon Shin, Youngkyun Jeong, June-Hee Lee, Jaehyuk Choi, and Jung-Hoon Chun. “A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems.” Sensors 18, no. 8 (August 17, 2018): 2709. doi:10.3390/s18082709.
Version
Final published version
Abstract
© 2018 by the authors. Licensee MDPI, Basel, Switzerland. We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The direct current (DC)-coupled receiver front-end circuits manage the common-mode level variations and compensate for the channel loss. The tracked oversampling clock and data recovery (CDR), which realizes fast lock acquisition below 1 baud period and low logic latency, is shared by the two channels. Fabricated in a 65-nm low-power complementary metal-oxide semiconductor (CMOS) technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43 mW from a 1.2-V power supply.
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Creative Commons Attribution 4.0 International license
Persistent DSpace Link
DOI of Published Version
http://dx.doi.org/10.3390/s18082709
