A Fast Multiport Memory Based on Single-port Memory Cells
Name
MIT-LCS-TM-455.pdf
Size
3.59 MB
Format
Adobe PDF
Checksum (MD5)
3fcf234a0897ec34b62421213be4969c
Author(s)
Rivest, Ronald L.
Glasser, L.
Date Issued
July 1991
Series/Report no.
MIT-LCS-TM-455
Abstract
We present a new design for dual-port memories that uses single-port memory cells but guarantees fast deterministic read/write access. The basic unit of storage is the word, rather than the bit, and addresses conflicts result in bit errors that are removed by correction circuitry. The addressing scheme uses Galois field arithmetic to guarantee that the maximum number of bit errors in any word accessed is one. These errors can be corrected every time with a simple correction scheme. The scheme can be generalized to an arbitrary number of ports.
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