Energy efficient RF communication systems for wireless microsensors
Name
51548132-MIT.pdf
Description
Full printable version
Size
10.41 MB
Format
Adobe PDF
Checksum (MD5)
8ed16f09ae4f315319b87f5127d264f0
Author(s)
Cho, SeongHwan, 1974-
Advisor(s)
Anantha Chandrakasan.
Alternative Title
Energy efficient radio frequency communication systems for wireless microsensors
Date Issued
2002
Publisher
Massachusetts Institute of Technology
Abstract
Emerging distributed wireless microsensor networks will enable the reliable and fault tolerant monitoring of the environment. Microsensors are required to operate for years from a small energy source while maintaining a reliable communication link to the base station. In order to reduce the energy consumption of the sensor network, two aspects of the system design hierarchy are explored: design of the communication protocol and implementation of the RF transmitter. In the first part of the thesis, energy efficient communication protocols for a coordinated static sensor network are proposed. A detailed communication energy model, obtained from measurements, is introduced that incorporates the non-ideal behavior of the physical layer electronics. This includes the frequency errors and start-up energy costs of the radio, which dominate energy consumption for short packet, low duty cycle communication. Using this model, various communication protocols are proposed from an energy perspective, such as MAC protocols, bandwidth allocation methods and modulation schemes. In the second part of the thesis, design methodologies for an energy efficient transmitter are presented for a low power, fast start-up and high data rate radio.
(cont.) The transmitter is based on a [Epsilon]-[Delta] fractional-N synthesizer that exploits trade-offs between the analog and digital components to reduce the power consumption. The transmitter employs closed loop direct VCO modulation for high data rate FSK modulation and a variable loop bandwidth technique to achieve fast start-up time. A prototype transmitter that demonstrates these techniques is implemented using 0.25[mu]m CMOS. The test chip achieves 20[mu]s is start-up time with an effective data rate of 2.5Mbps while consuming 22mW.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references (p. 131-137).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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