Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs
Author(s)
Zhao, Xin
Vardi, Alon
del Alamo, Jesus A
Date Issued
May 2017
Journal
IEEE Electron Device Letters
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Zhao, Xin et al. "Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs." IEEE Electron Device Letters 38, 7 (July 2017): 855 - 858 © 2017 IEEE
Version
Author's final manuscript
Abstract
This letter demonstrates top-down InGaAs/InAs heterojunction vertical nanowire tunnel FETs with sub-thermal subthreshold characteristics over two orders of magnitude of current. A minimal subthreshold swing of 53 mV/decade at V[subscript ds] = 0.3 V has been obtained at room temperature. An I[subscript 60] (defined as the highest current level where the subthreshold characteristics exhibit a transition from sub- to super-60 mV/decade behavior) of 4.3 nA/μm has been achieved at V s = 0.3 V. Compared with an earlier device generation, much reduced temperature dependence of the subthreshold characteristics is observed in this letter. The major difference between the two device generations is the drastically reduced interface trap density, evidenced by the improvement in the subthreshold swing of InGaAs vertical nanowire MOSFETs fabricated at the same time. This result suggests oxide-semiconductor interface trap-assisted tunnelling the main leakage mechanism in III-V TFETs fabricated by our process. The improvement in the interface quality has been enabled by improved gate oxide deposition and post-deposition treatment.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/led.2017.2702612
