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Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI

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Author(s)
Leighton, Frank Thomson
Advisor(s)
Miller, Gary L.
Date Issued
August 1982
Series/Report no.
MIT-LCS-TR-274
Abstract
The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include:1) an asymptotically optimal, (N /log N)-area layout for the N-node shuffle-exchange graph, and 2) several practical layouts for small shuffle-exchange graphs.
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