High-level specification and efficient implementation of pipelined circuits
Name
aspdac01.pdf
Description
Accepted version
Size
54.29 KB
Format
Adobe PDF
Checksum (MD5)
7cd79b984115ea0cd604ce53f71a5c64
Author(s)
Marinescu, M-C
Rinard, M
Date Issued
January 1, 2001
Journal
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
Publisher
IEEE
Citation
High-Level Specification and Efficient Implementation of Pipelined Circuits. Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001, January 30, 2001 - February 2, 2001. 2001. Institute of Electrical and Electronics Engineers Inc.
Version
Author's final manuscript
Abstract
© 2001 IEEE. This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/aspdac.2001.913384
