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  5. Demonstration system for a low power video compression integrated circuit

Demonstration system for a low power video compression integrated circuit

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Author(s)
Chotigavanich, Charatpong, 1975-
Advisor(s)
Anantha P. Chandrakasan.
Date Issued
2000
Publisher
Massachusetts Institute of Technology
Description
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Includes bibliographical references (leaf 56).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Persistent DSpace Link
http://hdl.handle.net/1721.1/86292
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