A time-interleaved Zero-Crossing-Based analog-to-digital converter
Name
725597567-MIT.pdf
Description
Full printable version
Size
8.05 MB
Format
Adobe PDF
Checksum (MD5)
51b8bb3d25b3522245260266cb2787b0
Author(s)
Chow, Albert C. (Albert Chin-Hoa), 1977-
Advisor(s)
Hae-Seung Lee.
Alternative Title
Time-interleaved ZCB analog-to-digital converter
Date Issued
2011
Publisher
Massachusetts Institute of Technology
Abstract
CMOS technology scaling has further reduced the output voltage swing and device gain, making it increasingly difficult to realize high-speed, high-gain op-amps with a stable feedback loop. The switched capacitor multiplier circuit in pipelined ADC is one application which has been hindered by op-amp limitations. Zero Crossing Based (ZCB) switched-capacitor topologies have been proposed as an alternative to op-amp based circuits because ZCB circuits do not suffer from the same CMOS scaling issues. This research applies ZCB techniques to Time Interleaved ADCs (TIADC). Mismatch between the individual ADCs, or channels, that make up the TIADC degrade its accuracy and is a fundamental design challenge. This research addresses the mismatch issue by investigating new circuit techniques to reduce offset error and timing skew. A new method to analyze noise in ZCB topologies is also presented. These methods were used to design a 2GS/S 8-bit time-interleaved, pipelined ZCB ADC. Although applied to ZCB ADCs, the timing skew correction topology and noise analysis method are applicable to other ADC topologies.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 195-198).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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