Leveraging latency-insensitivity to ease multiple FPGA design
Name
2012.02.isfpga.leap_multifpga.pdf
Description
Accepted version
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652.33 KB
Format
Adobe PDF
Checksum (MD5)
b1054ead6c8981143b207a52646394aa
Author(s)
Fleming, Kermin Elliott
Pellauer, Michael
Arvind, Arvind
Emer, Joel S
Date Issued
February 2012
Journal
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Publisher
Association for Computing Machinery (ACM)
Citation
Fleming, Kermin, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind and Joel Emer. "Leveraging latency-insensitivity to ease multiple FPGA design." In Proceeding FPGA '12 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, Monterey, California, USA, February 22-24, 2012, pages 175-184.
Version
Author's final manuscript
Abstract
Traditionally, hardware designs partitioned across multiple FPGAs have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete FPGAs. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple FPGAs using explicitly programmed latency-insensitive links. We describe the automatic synthesis of an area efficient, high performance network for routing these inter-FPGA links. By mapping a diverse set of large research prototypes onto a multiple FPGA platform, we demonstrate that our tool obtains significant gains in design feasibility, compilation time, and even wall-clock performance.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1145/2145694.2145725
