A compact superconducting nanowire memory element operated by nanowire cryotrons
Name
1711.08290.pdf
Description
Submitted version
Size
1.38 MB
Format
Adobe PDF
Checksum (MD5)
9b13156f623ec47a65ce86bd2e933171
Author(s)
Zhao, Qing-Yuan
Toomey, Emily Anne
Butters, Brendan Andrew
McCaughan, Adam N.
Dane, Andrew E.
Nam, Sae-Woo
Berggren, Karl K.
Date Issued
February 2018
Journal
Superconductor Science and Technology
Publisher
IOP Publishing
Citation
Zhao, Qing-Yuan, et al. “A Compact Superconducting Nanowire Memory Element Operated by Nanowire Cryotrons.” Superconductor Science and Technology 31, 3 (July 2018): 035009.
Version
Original manuscript
Abstract
A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10[superscript -19] J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μm ×7 μm in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1088/1361-6668/AAA820
