Asynchronous data-dependent jitter compensation
Name
516191892-MIT.pdf
Description
Full printable version
Size
3.74 MB
Format
Adobe PDF
Checksum (MD5)
f1d329f255d29394a45c3ec979830b8b
Author(s)
Price, Michael, Ph. D. (Michael R.). Massachusetts Institute of Technology
Advisor(s)
Vladimir M. Stojanovic and Michael St. Germain.
Date Issued
2009
Publisher
Massachusetts Institute of Technology
Abstract
Data-dependent jitter (DDJ) caused by lossy channels is a limiting factor in the bit rates that can be achieved reliably over serial links. This thesis explains the causes of DDJ and existing equalization techniques, then develops an asynchronous (clock-agnostic) architecture for DDJ compensation. The compensation circuit alters the transition times of a digital signal to cancel the expected channel-induced delays. It is designed for a 0.35 [mu]m BiCMOS process with a 240 x 140 ¹m footprint and typically consumes 3.4 mA, a small fraction of the current used in a typical transmitter. Extensive simulations demonstrate that the circuit has the potential to reduce channel-induced DDJ by at least 50% at bit rates of 6.25 Gb/s and 10 Gb/s.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 95-96).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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