A 4th order continuous-time [Delta] [Epsilon] ADC with VCO-based integrator and quantizer
Name
428817944-MIT.pdf
Description
Full printable version
Size
30.4 MB
Format
Adobe PDF
Checksum (MD5)
7685470a108f25130b2b0e7d4daad85f
Author(s)
Park, Matthew Jeremiah
Advisor(s)
Michael H. Perrott.
Alternative Title
Fourth order continuous-time [Delta] [Epsilon] ADC with VCO-based integrator and quantize
Date Issued
2009
Publisher
Massachusetts Institute of Technology
Abstract
The use of a VCO-based integrator and quantizer within a continuous-time (CT) [Delta] [Epsilon] analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 [mu]m CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADC's, which exclusively made use of the output frequency. Furthermore, the proposed architecture includes a scheme for performing fast dynamic element matching (DEM), enabling first-order shaping of unit-element mismatch in all feedback DAC's.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
In title on title page, "[Delta]" and "[Epsilon]" appear as upper-case Greek letters.
Includes bibliographical references (p. 135-140).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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