Bandwidth steering in HPC using silicon nanophotonics
Name
sip_hpc_sc2019.pdf
Description
Accepted version
Size
3.54 MB
Format
Adobe PDF
Checksum (MD5)
63d53151ecc4edaf8c2c39758157cad8
Author(s)
Ghobadi, Manya
Date Issued
November 2019
Journal
International Conference for High Performance Computing, Networking, Storage and Analysis, SC
Publisher
Association for Computing Machinery (ACM)
Citation
Michelogiannakis, George et al. “Bandwidth steering in HPC using silicon nanophotonics.” International Conference for High Performance Computing, Networking, Storage and Analysis, SC, 2019 (November 2019): 17–22 © 2019 The Author(s)
Version
Author's final manuscript
Abstract
As bytes-per-FLOP ratios continue to decline, communication is becoming a bottleneck for performance scaling. This paper describes bandwidth steering in HPC using emerging reconfigurable silicon photonic switches. We demonstrate that placing photonics in the lower layers of a hierarchical topology efficiently changes the connectivity and consequently allows operators to recover from system fragmentation that is otherwise hard to mitigate using common task placement strategies. Bandwidth steering enables efficient utilization of the higher layers of the topology and reduces cost with no performance penalties. In our simulations with a few thousand network endpoints, bandwidth steering reduces static power consumption per unit throughput by 36% and dynamic power consumption by 14% compared to a reference fat tree topology. Such improvements magnify as we taper the bandwidth of the upper network layer. In our hardware testbed, bandwidth steering improves total application execution time by 69%, unaffected by bandwidth tapering.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1145/3295500.3356145
