A timeshared, runtime reconfigurable hardware co-processing architecture
Name
505532150-MIT.pdf
Description
Full printable version
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34.47 MB
Format
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Checksum (MD5)
f51bceb6f616736ccc5bdf3a670c656c
Author(s)
Gelb, Benjamin S
Advisor(s)
Christopher J. Terman.
Date Issued
2009
Publisher
Massachusetts Institute of Technology
Abstract
The constant desire for increased performance in microprocessor systems has led to the need for specialized hardware cores to accelerate specific computational tasks. In this thesis, we explore the potential of using FPGA partial reconfiguration to create a platform for customized hardware cores that may be loaded on demand, at runtime, and replaced when not in use. We implement two new software tools, bitparse and bitrender, to demonstrate the bitstream relocation technique. Further, we present a functional microprocessor system coupled with a runtime reprogramable peripheral synthesized on a Xilinx Virtex-5 FPGA and discuss its performance implications.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
Includes bibliographical references (leaves 73-74).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
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