The prospects for 10 nm III-V CMOS
Name
del Alamo VLSI-TSA 2010.pdf
Size
191.39 KB
Format
Adobe PDF
Checksum (MD5)
34bf91ab9511651c20ac99715a844bf4
Author(s) •
del Alamo, Jesus A.
Kim, D.-H.
Date Issued
April 2010
Journal
International Symposium on VLSI Technology Systems and Applications (VLSI-TSA), 2010
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
del Alamo, J. A., and D.-H. Kim. “The prospects for 10 nm III-V CMOS.” IEEE, 2010. 166-167.
Version
Author's final manuscript
Abstract
The increasing difficulties for further scaling down of Si CMOS is bringing to the fore the investigation of alternative channel materials. Among these, III-V compound semiconductors are very attractive due to their outstanding electron transport properties. This paper briefly reviews the prospects and the challenges for a III-V CMOS technology with gate lengths in the 10 nm range.
MIT Department
Massachusetts Institute of Technology. Microsystems Technology Laboratories
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike 3.0
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/VTSA.2010.5488901