Application of three-dimensional circuit integration to global clock distribution
Name
57175032-MIT.pdf
Description
Full printable version
Size
420.64 KB
Format
Adobe PDF
Checksum (MD5)
7548c3450d27714e87709c041dcca92b
Author(s)
Salinas, Erica M. (Erica Marie), 1980-
Advisor(s)
Jim Burns and Rafael Reif.
Date Issued
2004
Publisher
Massachusetts Institute of Technology
Abstract
As the semi-conductor industry moves towards deep sub-micron designs, efficiency of chip-wide communication is becoming the limiting factor on system performance. One globally distributed signal with significant effect on system performance is the clock signal. In this paper utilization of three-dimensional circuit integration to reduce the negative effects of technology scaling on clock signal distribution is investigated. A design is proposed that removes the clock distribution network from the same active plane as the logical functions of the system and places them on a separate, but electrically connected active plane. Proposed benefits of a three-dimensional distribution network are the reduction of global skew, greater signal integrity, and an increase in system density. All aspects of the design process are detailed including methodology, simulation tools and verification, interconnect and repeater design, the three-dimensional integration process, and the overall predicted system benefits.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2004.
Includes bibliographical references (leaf 35).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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