A reference model for the PIPE security coprocessor
Name
1227507647-MIT.pdf
Size
364.65 KB
Format
Adobe PDF
Checksum (MD5)
b90ff43d1a3a8377b42fc4cad4446887
Author(s)
Ortiz, Baltazar(Baltazar G.)
Advisor(s)
Howard E. Shrobe.
Alternative Title
Reference model for the Processor Interlocks for Policy Enforcement security coprocessor
Date Issued
2020
Publisher
Massachusetts Institute of Technology
Abstract
Systematic security solutions implemented at the hardware level offer higher performance than similar software approaches and are harder to attack or bypass. While hardware changes are generally more difficult to integrate into existing systems, the PIPE (Processor Interlocks for Policy Enforcement) coprocessor architecture requires no major changes to the AP (Application Processor) that it runs alongside, which facilitates the integration process. The PIPE provides the ability to enforce a wide variety of security policies utilizing the metadata that it stores for each word of memory and each register on the AP. In this thesis, we define and implement a reference model for the PIPE using the Chisel hardware design language, resulting in an accessible platform for future evaluation and research.
Description
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, September, 2020
Cataloged from student-submitted PDF of thesis.
Includes bibliographical references (pages 55-58).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
MIT theses may be protected by copyright. Please reuse MIT thesis content according to the MIT Libraries Permissions Policy, which is available through the URL provided.
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