Modern Trends in Microelectronics Packaging Reliability Testing
Name
micromachines-15-00398.pdf
Size
1.94 MB
Format
Adobe PDF
Checksum (MD5)
e2bbb27560a2a092a7bd6770318502ae
Author(s)
Bender, Emmanuel
Bernstein, Joseph B.
Boning, Duane S.
Date Issued
March 15, 2024
Journal
Micromachines
Publisher
MDPI AG
Citation
Micromachines 15 (3): 398 (2024)
Version
Final published version
Abstract
In this review, recent trends in microelectronics packaging reliability are summarized. We review the technology from early packaging concepts, including wire bond and BGA, to advanced techniques used in HI schemes such as 3D stacking, interposers, fan-out packaging, and more recently developed silicon interconnect fabric integration. This review includes approaches for both design modification studies and packaged device validation. Methods are explored for compatibility in new complex packaging assemblies. Suggestions are proposed for optimizations of the testing practices to account for the challenges anticipated in upcoming HI packaging schemes.
Subjects
Electrical and Electronic Engineering
Mechanical Engineering
Control and Systems Engineering
MIT Department
Massachusetts Institute of Technology. Microsystems Technology Laboratories
Terms of Use
Creative Commons Attribution
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.3390/mi15030398
