We are experiencing minor difficulties with our submission forms, which we are working to resolve. If you have any issues while submitting items, please contact us at dspace-lib@mit.edu.

A Timing Analysis and Optimization System for Level-clocked Circuitry

Thumbnail Image
Download
Name

MIT-LCS-TR-605.pdf

Size

8.81 MB

Format

Adobe PDF

Checksum (MD5)

bc6d95cfc0c89828c95044b9364dbe04

Author(s)
Papaefthymiou, Marios Christos
Advisor(s)
Leiserson, Charles E.
Date Issued
September 1993
Series/Report no.
MIT-LCS-TR-605
Abstract
This thesis investigates timing analysis and optimization issues in synchronous circuitry. The major thrust of our work is a collection of provably correct and efficient algorithms that perform a variety of architectural-level operations on level-clocked
Persistent DSpace Link
PrivacyPermissionsAccessibilityContact us
Notify us about copyright concerns.