A CMOS Imager With a Programmable Bit-Serial Column-Parallel SIMD/MIMD Processor
Name
Yamashita-2009-A CMOS Imager With a Programmable Bit-Serial Column-Parallel SIMDMIMD Processor.pdf
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742.4 KB
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Checksum (MD5)
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Author(s)
Yamashita, Hirofumi
Sodini, Charles G.
Date Issued
October 2009
Journal
IEEE Transactions on Electron Devices
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Yamashita, Hirofumi, and Charles G. Sodini. “A CMOS Imager With a Programmable Bit-Serial Column-Parallel SIMD/MIMD Processor.” IEEE Transactions on Electron Devices 56.11 (2009): 2534–2545. © Copyright 2009 IEEE
Version
Final published version
Abstract
An imager with an integrated fully programmable bit-serial column-parallel processor is proposed to meet the demand for a compact and versatile system-on-imager chip for consumer applications. The on-imager processor is targeting a computationally intensive low-level image processing task. The processor is physically arranged as a densely packed 2-D processing element (PE) array at an imager column level. The digital processor has a multiple-instruction-multiple-data (MIMD) architecture configuring multiple column-parallel single-instruction-multiple-data (SIMD) processors. The prototype imager chip with 128 times 128 pixels and 4 times 128 PE array designed with 0.6-mum technology was fabricated, and its functionality was tested. The estimation of performance level of the proposed processor architecture with an advanced technology such as the 0.09-mum process technology shows that the proposed imager chip architecture has a potential of giga sum operations per second per square millimeter class processing performance.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/ted.2009.2030718
