A hardware spinal decoder
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Balakrishnan_A hardware.pdf
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Author(s)
Iannucci, Peter A.
Fleming, Kermin Elliott
Perry, Jonathan
Balakrishnan, Hari
Shah, Devavrat
Date Issued
October 2012
Journal
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems (ANCS '12)
Publisher
Association for Computing Machinery (ACM)
Citation
Peter A. Iannucci, Kermin Elliott Fleming, Jonathan Perry, Hari Balakrishnan, and Devavrat Shah. 2012. A hardware spinal decoder. In Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems (ANCS '12). ACM, New York, NY, USA, 151-162.
Version
Author's final manuscript
Abstract
Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as greatly reduced latency and complexity. The enabling architectural feature is a novel alpha-beta incremental approximate selection algorithm. We also present a method for obtaining hints which anticipate successful or failed decoding, permitting early termination and/or feedback-driven adaptation of the decoding parameters.
We have validated our implementation in FPGA with on-air testing. Provisional hardware synthesis suggests that a near-capacity implementation of spinal codes can achieve a throughput of 12.5 Mbps in a 65 nm technology while using substantially less area than competitive 3GPP turbo code implementations.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1145/2396556.2396593
